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PRELIMINARY PRODUCT SPECIFICATION
1
Z86E30/E31/E40
Z8 4K OTP MICROCONTROLLER
FEATURES
Device Z86E30 Z86E31 Z86E40 ROM (KB) 4 2 4 RAM* (Bytes) 237 125 236 I/O Lines 24 24 32 Speed (MHz) 16 16 16
s
1
Note: *General-Purpose s s s
Programmable OTP Options: RC Oscillator EPROM Protect Auto Latch Disable Permanently Enabled WDT Crystal Oscillator Feedback Resistor Disable RAM Protect Low-Power Consumption: 60 mW Fast Instruction Pointer: 0.75 s Two Standby Modes: STOP and HALT Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive
Standard Temperature (VCC = 3.5V to 5.5V) Extended Temperature (VCC = 4.5V to 5.5V) Available Packages: 28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only) 28-Pin DIP Window (Z86E30/31 only) 40-Pin DIP OTP/Window (Z86E40 only) 44-Pin PLCC/QFP OTP (Z86E40 only) 44-Pin PLCC Window (Z86E40 only) Software Enabled Watch-Dog Timer (WDT)
s s s s s s
s s
s
Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2
s
s s s
24/32 Input/Output Lines
s
Auto Latches Auto Power-On Reset (POR)
GENERAL DESCRIPTION
The Z86E30/E31/E40 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip Z8(R) MCU family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has access to three additional control registers that allow easy access to register mapped peripheral and I/O circuits. For applications demanding powerful I/O capabilities, the Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and par-
DS97Z8X0500
PRELIMINARY
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Z86E30/E31/E40 Z8 4K OTP Microcontroller allel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All Signals with a preceding front slash, "/", are active Low, for example, B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Zilog Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
(E40 Only) VCC
Output Input
GND
XTAL /AS /DS R//W /RESET
Port 3
Machine Timing & Instruction Control RESET WDT POR ,
Counter/ Timers (2)
ALU
FLAGS Interrupt Control Register Pointer Register File Program Counter OTP
Two Analog Comparators
Port 2
Port 0
Port 1
4 I/O (Bit Programmable)
4
8 Address/Data or I/O (Byte Programmable) (E40 Only)
Address or I/O (Nibble Programmable)
Figure 1. Z86E30/E31/E40 Functional Block Diagram
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
D7 - 0
1
AD 11- 0 Z8 MCU MSN Port 3 Address MUX D7 - 0 AD 11- 0 EPROM Data MUX D7 - 0 Z8 Port 2 AD 11- 0
TEST ROM Z8 Port 0 OTP Options PGM + T est Mode Logic VPP P33 EPM P32 /CE XT1 /PGM P30
/OE P31
Figure 2. EPROM Programming Block Diagram
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PIN IDENTIFICATION
Table 1. 40-Pin DIP Pin Identification Standard Mode
R//W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 /AS 1 40 /DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 /RESET
Pin # 1 2-4 5-7 8-9 10 11 12-13 14 15 16-18 19 20 21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40
Symbol R//W P25-P27 P04-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 /AS /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-P24 /DS
Function Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe
Direction Output In/Output In/Output In/Output In/Output In/Output Output Input Input Output Output Input Output Output Output Input In/Output In/Output In/Output In/Output In/Output In/Output Output
40-Pin DIP
20
21
Figure 3. 40-Pin DIP Pin Configuration* Standard Mode
Notes: *Pin Configuration and Identification identical on DIP and Cerdip Window Lid style packages.
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04
7
P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00
1
P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
6
1
40 39
44-Pin PLCC
17 18
29 28
Figure 4. 44-Pin PLCC Pin Configuration Standard Mode
Table 2. 44-Pin PLCC Pin Identification Pin # 1-2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23-24 25-26 27 28 29-31 32 Symbol GND P12-P13 P03 P20-P24 /DS NC R//W P25-P27 P04-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P33 P34 Function Direction Pin # 33 34 35 36 37 38 39 40-41 42-43 44
P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1
Table 2. 44-Pin PLCC Pin Identification Symbol /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 Function Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Direction Output Input Input Output Output Output Input In/Output In/Output In/Output
Ground Port 1, Pins 2,3 In/Output Port 0, Pin 3 In/Output Port 2, Pins In/Output 0,1,2,3,4 Data Strobe Output No Connection Read/Write Output Port 2, Pins 5,6,7In/Output Port 0, Pins 4,5,6In/Output Port 1, Pins 4,5 In/Output Port 0, Pin 7 In/Output Power Supply Port 1, Pins 6,7 In/Output Crystal Oscillator Output Crystal Oscillator Input Port 3, Pins 1,2,3Input Port 3, Pin 4 Output
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33 P21 P22 P23 P24 /DS NC R//W P25 P26 P27 P04 34
P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00 23 22
44-Pin QFP
44 1
12 11
P30 P36 P37 P35 /RESET R//RL /AS P34 P33 P32 P31
Figure 5. 44-Pin QFP Pin Configuration Standard Mode
Table 3. 44-Pin QFP Pin Identification Pin # 1-2 3-4 5 6-7 8-9 10 11 12-14 15 16 17 18 19 20 21 22 23-24 25-26 Symbol Function P05-P06 P14-P15 P07 VCC P16-P17 XTAL2 XTAL1 P31-P13 P34 /AS R//RL /RESET P35 P37 P36 P30 P00-P01 P10-P11 Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pins 0,1 Direction In/Output In/Output In/Output In/Output Output Input Input Output Output Input Input Output Output Output Input In/Output In/Output Pin # 27 28-29 30-31 32 33-37 38 39 40 41-43 44
P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1
Table 3. 44-Pin QFP Pin Identification Symbol Function P02 GND P12-P13 P03 P20-4 /DS NC R//W P25-P27 P04 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 Direction In/Output In/Output In/Output In/Output Output Output In/Output In/Output
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Table 4. 40-Pin DIP Package Pin Identification EPROM Mode
NC D5 D6 D7 A4 A5 A6 NC NC A7 VCC NC NC NC /CE /OE EPM VPP A8 NC 1 40 NC D4 D3 D2 D1 D0 A3 NC NC GND A2 NC NC A1 A0 /PGM A10 A11 A9 NC
Pin # 1 2-4 5-7 8-9 10 11 12-14 15 16 17 18 19 20-21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40
Symbol NC D5-D7 A4-A6 NC A7 VCC NC /CE /OE EPM VPP A8 NC A9 A11 A10 /PGM A0-A1 NC A2 GND NC A3 D0-D4 NC
Function No Connection Data 5,6,7 Address 4,5,6 No Connection Address 7 Power Supply No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode Address 0,1 No Connection Address 2 Ground No Connection Address 3 Data 0,1,2,3,4 No Connection
Direction In/Output Input Input
1
40-Pin DIP
Input Input Input Input Input Input Input Input Input Input Input
20
21
Figure 6. 40-Pin DIP Pin Configuration* EPROM Mode
Input In/Output
Note: *Pin Configuration and Description identical on DIP and Cerdip Window Lid style packages.
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D1 D2 D3 D4 NC NC NC D5 D6 D7 A4
7
D0 A3 NC NC GND GND A2 NC NC A1 A0 6 1 40 39
44 -Pin PLCC
17 18
29 28
/PGM A10 A11 A9 NC NC NC A8 VPP EPM /OE
Figure 7. 44-Pin PLCC Pin Configuration EPROM Programming Mode
Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # 1-2 3-4 5 6-10 11-13 14-16 17-19 20-21 22 23-24 25-27 28 29 30 Symbol GND NC A3 D0-D4 NC D5-D7 A4-A6 NC A7 VCC NC /CE /OE EPM Function Ground No Connection Address 3 Data 0,1,2,3,4 No Connection Data 5,6,7 Address 4,5,6 No Connection Address 7 Power Supply No Connection Chip Select Output Enable EPROM Prog. Mode Direction Pin # 31 Input In/Output In/Output Input Input 32 33-35 36 37 38 39 40-41 42-43 44
A5 A6 NC NC A7 VCC VCC NC NC NC /CE
Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Symbol VPP A8 NC A9 A11 A10 /PGM A0,A1 NC A2 Function Prog. Voltage Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode Address 0,1 No Connection Address 2 Direction Input Input Input Input Input Input Input Input
Input Input Input
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33 D1 D2 D3 D4 NC NC NC D5 D6 D7 A4 34
D0 A3 NC NC GND GND A2 NC NC A1 A0
1
/PGM A10 A11 A9 NC NC NC A8 VPP EPM /OE
23 22
44 -Pin QFP
44 1
12 11
Figure 8. 44-Pin QFP Pin Configuration EPROM Programming Mode
Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode Pin # 1-2 3-4 5 6-7 8-10 11 12 13 14 15 16-18 19 20 21 22 Symbol A5-A6 NC A7 VCC NC /CE /OE EPM VPP A8 NC A9 A11 A10 /PGM Function Address 5,6 No Connection Address 7 Power Supply No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode Direction Input Input Pin # 23-24 25-26 27 28-29 30-31 32 33-37 38-40 41-43 44
A5 A6 NC NC NC A7 VCC VCC NC NC /CE
Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode Symbol A0,A1 NC A2 GND NC A3 D0-D4 NC D5-D7 A4 Function Address 0,1 No Connection Address 2 Ground No Connection Address 3 Data 0,1,2,3,4 No Connection Data 5,6,7 Address 4 Direction Input Input
Input Input Input Input Input Input Input Input Input
Input In/Output In/Output Input
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P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34
1
28
28-Pin DIP
14
15
P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35
D5 D6 D7 A4 A5 A6 A7 VCC NC /CE /OE EPM VPP A8
1
28
28-Pin DIP
14
15
D4 D3 D2 D1 D0 A3 VSS A2 A1 A0 /PGM A10 A11 A9
Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration*
Figure 10. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration*
Table 7. 28-Pin DIP/SOIC/PLCC Pin Identification* Pin # 1-3 4-7 8 9 10 11-13 14-15 16 17 18 19-21 22 23 24-28 Symbol P25-P27 P04-P07 VCC XTAL2 XTAL1 P31-P33 P34-P35 P37 P36 P30 P00-P02 VSS P03 P20-P24 Function Direction
P04 P27 P26 P25 P24 P23 P22 4 XXX P05 XXX P06 XXX P07 VCC XXX XXX XT2 XXX XT1 XXX P31 5 1 26 25
Port 2, Pins 5,6, In/Output Port 0, Pins 4,5,6,7 In/Output Power Supply Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Output Input Input Output Output Output Input In/Output In/Output In/Output
28-Pin PLCC
11 12
19 18
P21 XXX P20 XXX P03 XXX VSS XXX P02 XXX P01 XXX P00 XXX
Notes: *Pin Identification and Configuration identical on DIP and Cerdip Window Lid style packages.
Figure 11. Standard Mode 28-Pin PLCC Pin Configuration
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P32 P33 P34 P35 P37 P36 P30
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Table 8. 28-Pin EPROM Pin Identification* Pin # 1-3 4-7 8
D1 XXX D0 XXX A3 XXX VSS XXX A2 XXX A1 XXX A0 XXX A4 D7 D6 D5 D4 D3 D2
Symbol D5-D7 A4-A7 VCC NC /CE /OE EPM VPP A8-A9 A11 A10 /PGM A0-A2 VSS A3 D0-D4
Function Data 5,6,7 Address 4,5,6,7 Power Supply No connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage Address 8,9 Address 11 Address 10 Prog. Mode Address 0,1,2 Ground Address 3 Data 0,1,2,3,4
Direction In/Output Input
1
4 XXX A5 XXX A6 XXX A7 VCC XXX XXX NC XXX /CE XXX /OE 5
1
26 25
28-Pin PLCC
9 10 11 12 13 14-15 16 17 18 19-21 22 23 24-28
Input Input Input Input Input Input Input Input Input Input In/Output
11 12
19 18
Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration
EPM VPP A8 A9 A11 A10 /PGM
Notes: *Pin Identification and Configuration identical on DIP and Cerdip Window Lid style packages.
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on XTAL1 and /RESET Pins with Respect to VSS [Note 2] Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sinkedd by /RESET Pin
Notes: 1. This applies to all pins except XTAL pins and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state.
Min -40 -65 -0.6 -0.3 -0.6
Max +105 +150 +7 +7 V DD+1 1.21 220 180
Units C C V V V W mA mA A A mA mA
-600 -600
+600 +600 25 25 3 mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Total power dissipation should not exceed 1.2 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ I DD - (sum of IOH) ] + sum of [ (V DD - VOH) x IOH ] + sum of (V0L x I0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load).
From Output Under Test
150 pF
Figure 13. Test Load Diagram
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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DC ELECTRICAL CHARACTERISTICS
TA= 0 C to +70 C Sym VCH VCL VIH VIL VOH VOH1 VOL VOL1 VOL2 VRH VRL VOLR VOFFSET VICR IIL IOL IIR Parameter Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Low EMI Mode Output High Voltage Output Low Voltage Low EMI Mode Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Reset Output Low Voltage Comparator Input Offset Voltage Input Common Mode Voltage Range Input Leakage Output Leakage Reset Input Current VCC Note [3] 3.5V 5.5V 3.5V 4.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 4.5V 3.5V 4.5V 3.5V 4.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 4.5V 3.5V 5.5V 3.5V 4.5V 3.5V 4.5V 3.5V 4.5V .8 VCC .8 VCC GND -0.3 GND -0.3 Min 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC -0.4 VCC-0.4 VCC-0.4 0.4 0.4 0.4 0.4 1.2 1.2 VCC VCC 0.2 VCC 0.2 VCC 0.6 0.6 25 25 VCC -1.0V VCC -1.0V 2 2 2 2 -130 -180 Max VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC Typical @ 25C 1.8 2.5 0.9 1.5 2.5 2.5 1.5 1.5 3.3 4.8 3.3 4.8 0.2 0.2 0.1 0.1 0.5 0.5 1.7 2.1 1.3 1.7 0.3 0.2 10 10 Units V V V V V V V V V V V V V V V V V V V V V V V V mV mV V V A A A A A A 13 VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC IOL = 1.0 mA IOL = 1.0 mA 13 IOH = - 0.5 mA IOH = -2.0 mA IOH = -2.0 mA IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = + 4.0 mA IOL = + 12 mA IOL = + 12 mA 8 8 8 8 Conditions Driven by External Clock Generator Driven by External Clock Generator Notes
0 0 -1 -1 -1 -1 -20 -20
10 10
0.032 0.032 0.032 0.032 -65 -112
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Z86E30/E31/E40 Z8 4K OTP Microcontroller TA= 0 C to +70 C Sym ICC ICC1 Parameter Supply Current Standby Current Halt Mode VCC Note [3] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 0.7 1.4 -0.6 -1 3.0 2.0 2.3 Min Max 20 25 8 8 7.0 7.0 10 10 800 800 8 15 -5 -8 24 13 3.1 Typical @ 25C 7 20 3.7 3.7 2.9 2.9 2 3 600 600 2.4 4.7 -1.8 -3.8 7 4 2.9 Units mA mA mA mA mA mA A A A A A A A A ms ms V Conditions @ 16 MHz @ 16 MHz VIN = 0V, VCC @ 16 MHz Clock Divide by 16 @ 16 MHz VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 0V Zilog
Notes 4,5 4,5 4,5 4,5 4,5 4,5 6,11 6,11 6,11,14 6,11,14 9 9 9 9
ICC2
Standby Current Stop Mode
IALL IALH TPOR VLV
Auto Latch Low Current Auto Latch High Current Power On Reset Auto Reset Voltage
1,7
Notes: 1. Device does not function down to the Auto Reset voltage 2. GND=0V 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1= CL2 = 22 pF 6. Same as note [4] except inputs at V CC 7. Max. temperature is 70C 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating 12. Typicals are at VCC = 5.0V and VCC = 3.5V 13. Z86C40 only 14. WDT running
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Zilog TA=-40 C to +105 C Sym VCH VCL VIH VIL VOH Parameter Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Low EMI Mode Output High Voltage Output Low Voltage Low EMI Mode Output Low Voltage Output Low Voltage Reset Input High Voltage Reset Output Low Voltage VCC Note [3] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 4.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 3.5V 5.5V 3.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V ICC2 IALL Standby Current (Stop Mode) Auto Latch Low Current 4.5V 5.5V 4.5V 5.5V 1.4 1.4 .8 VCC .8 VCC Min 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 0.7 VCC 0.7 VCC GND-0.3 GND-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.4 0.4 0.4 0.4 1.2 1.2 VCC VCC 0.6 0.6 25 25 VCC-1.5V VCC-1.5V 2 2 2 2 -180 -180 25 25 8 8 10 10 20 20 10 10 Max VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC Typical @ 25C 2.5 2.5 1.5 1.5 2.5 2.5 1.5 1.5 4.8 4.8 4.8 4.8 0.2 0.2 0.1 0.1 0.5 0.5 1.7 2.1 0.3 0.2 Units V V V V V V V V V V V V V V V V V V V V V V mV mV V V <1 <1 <1 <1 -112 -112 20 20 3.7 3.7 2 3 4.7 4.7 A A A A A A mA mA mA mA A A A A
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Conditions Driven by External Clock Generator Driven by External Clock Generator
Notes
1
IOH = - 0.5 mA IOH = - 0.5 mA IOH = -2.0 mA IOH = -2.0 mA IOL = 1.0 mA IOL = 1.0 mA IOL = + 4.0 mA IOL = +4.0 mA IOL = + 12 mA IOL = + 12 mA
8 8 8 8
VOH1 VOL VOL1 VOL2 VRH VOLR
8 8 8 8 13 13
IOL = 1.0 mA IOL = 1.0 mA
13 13
VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range Input Leakage IIL IOL IIR ICC ICC1 Output Leakage Reset Input Current Supply Current Standby Current Halt Mode
0 0 -1 -1 -1 -1 -18 -18
10 10 VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC
@ 16 MHz @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC VIN = 0V, VCC 0V < VIN < VCC 0V < VIN < VCC
4,5 4,5 4,5 4,5 6,11,14 6,11,14 9 9
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Z86E30/E31/E40 Z8 4K OTP Microcontroller TA=-40 C to +105 C Sym IALH TPOR VLV
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Zilog
Parameter Auto Latch High Current Power On Reset Auto Reset Voltage
VCC Note [3] 4.5V 5.5V 4.5V 5.5V
Min -1.0 -1.0 2.0 2.0 2.0
Max -10 -10 14 14 3.3
Typical @ 25C -3.8 -3.8 4 4 2.9
Units A A mS mS V
Conditions 0V < VIN < VCC 0V < VIN < VCC
Notes 9 9
1
Device does not function down to the Auto Reset voltage GND=0V The VCC voltage spec. of 5.5V guarantees 5.0V +/- 0.5V All outputs unloaded, I/O pins floating, inputs at rail CL1= CL2 = 22 pF Same as note [4] except inputs at V CC Max. temperature is 70C STD Mode (not Low EMI Mode) Auto Latch (mask option) selected For analog comparator inputs when analog comparators are enabled Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating Typicals are at VCC = 5.0V Z86C40 only WDT is not running
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
R//W , /DM
1
13 12 19
Port 0
16 18 3
20
Port 1
A7 - A0
D7 - D0 IN
1
2
9
/AS
8 4 5 6 11
/DS (Read)
17
10
Port1
A7 - A0
D7 - D0 OUT
14 7
15
/DS (W rite)
Figure 14. External I/O or Memory Read/Write Timing Z86C40 Only
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17
Z86E30/E31/E40 Z8 4K OTP Microcontroller TA = 0C to 70C 16 MHz No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAS(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) ThDS(AS) Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay /DM Valid to /AS Fall Delay /DS Valid to Address Valid Hold Time Note [3] VCC 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min 25 25 35 35 180 180 40 40 0 0 135 135 80 80 75 75 0 0 50 50 35 35 25 25 35 35 55 55 35 35 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Zilog
Notes 2 2 1,2 2
1,2 1,2 1,2 2 2 2 2 2 2 2 1,2 2 2
25 25
230 230 45 45 30 30 35 35
Notes: 1. When using extended memory timing add 2 TpC 2. Timing numbers given are for minimum TpC 3. The VCC voltage specification of 5.5V guarantees 5.0V +/- 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller TA = -40C to 105C 16 MHz Note [3] VCC Min Max 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 25 25 35 35 180 180 40 40 0 0 135 135 80 80 75 75 0 0 50 50 35 35 25 25 35 35 55 55 35 35
No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20
Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAS(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) ThDS(AS)
Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay /DM Valid to /AS Fall Delay /DS Valid to Address Valid Hold Time
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes 2 2 1,2 2
1
1,2 1,2 1,2 2 2 2 2 2 2 2 1,2 2 2
25 25
230 230 45 45 30 30 35 35
Notes: 1. When using extended memory timing add 2 TpC 2. Timing numbers given are for minimum TpC 3. The VCC voltage specification of 5.5V guarantees 5.0V +/- 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
1
3
Clock
2 7 7
2
3
TIN
4 6 5
IRQN
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Figure 15. Additional Timing Diagram
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Additional Timing Table (Divide-By-One Mode)
TA = 0 C to +70 C 4 MHz No 1 2 3 4 5 6 7 8A 8B 9 10 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min 250 250 Max DC DC 25 25 TA = -40 C to +105 C 4 MHz Min 250 250 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 4,8,9
1
100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC
100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC
11
TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time
ns ns ns ns
ns ns
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The VCC voltage specification of 5.5V guarantees 5.0V +/- 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver.
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Handshake Timing Diagrams
Data In
Data In Valid
Next Data In Valid
1 3
2
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Figure 16. Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Figure 17. Output Handshake Timing
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Additional Timing Table
TA = -40 C to +105 C 16 MHz No 1 2 3 4 5 6 7 8A 8B 9 10 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min 62.5 62.5 Max DC DC 15 15 Units ns ns ns ns ns ns ns ns Conditions Notes 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 [1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 4,8 4,8 4,8 4,8 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5,11
1
31 31 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 5TpC 12 12 5TpC 5TpC 10 5 20 10 40 20 160 80
11 12
TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time Twdt Watch-Dog Timer Delay Time Before Timeout
ns ns ns ns
ns ns
ms ms ms ms ms ms ms ms
D0 = 0 D1 = 0 D0 = 1 D1 = 0 D0 = 0 D1 = 1 D0 = 1 D1 = 1
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WDTMR 6. The VCC voltage spec. of 5.5V guarantees 5.0V +/- 0.5V 7. SMR D1 = 0 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
PIN FUNCTIONS EPROM Programming Mode
D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. A11-A0 Address Bus. During programming, the EPROM address is written to the address bus. VCC Power Supply. This pin must supply 5V during the EPROM read mode and 6V during other modes. /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. /PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. R//W Read/Write (output, write Low). The R//W signal is Low when the CCP is writing to the external program or data memory (Z86E40 only). /RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer reset, STOP-Mode Recovery, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. After the POR time, /RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z86E40 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after /RESET is released. For Power-On Reset, the reset output time is 5 ms. The Z86E40 does not reset WDTMR, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. /ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to VCC, the device functions normally as a Z8 ROM version). Note: When using in ROM Mode in High EMI (noisy) environment, the ROMless pins should be connected directly to VCC.
Application Precaution
The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on pins XTAL1 and /RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP, /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following:
s s
Using a clamping diode to VCC Adding a capacitor to the affected pin
Standard Mode
XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output.
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Zilog Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Either nibble output that can be globally programmed as push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 0 can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to Port 0's upper nibble. The lower nibble must have the same direction as the upper nibble. For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode. In ROM mode, Port 0 is defined as input after reset. Port 0 can be set in the High-Impedance Mode if selected as an address output state, along with Port 1 and the control signals /AS, /DS, and R//W (Figure 18).
Z86E30/E31/E40 Z8 4K OTP Microcontroller
1
DS97Z8X0500
PRELIMINARY
25
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
4 Port 0 (I/O) 4
Handshake Controls /DAV0 and RDY0 (P32 and P35)
Open-Drain OEN PAD
Out 1.5 In 2.3V Hysteresis
Auto Latch R 500 k
Figure 18. Port 0 Configuration
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DS97Z8X0500
Zilog Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOScompatible port with multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 1 can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls
Z86E30/E31/E40 Z8 4K OTP Microcontroller RDY1 and /DAV1 (Ready and Data Available). To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines (Figure 19). Port 1 can be placed in the high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the Z86E40 to share common resources in multiprocessor and DMA applications.
1
Port 2 (I/O) MCU
Handshake Controls /DAV1 and RDY1 (P33 and P34)
Open-Drain OEN
PAD
Out 1.5 In 2.3V Hysteresis
Auto Latch R 500 k
Figure 19. Port 1 Configuration (Z86E40 Only)
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as an input or output, independently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can
Zilog be globally programmed by the software. When used as an I/O port, Port 2 can be placed under handshake control. In Handshake Mode, Port 3 lines P31 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (Figure 20).
Port 2 (I/O) Z86E40 MCU
Handshake Controls /DAV2 and RDY2 (P31 and P36)
Open-Drain OEN
PAD
Out TTL Level Shifter In
Auto Latch R 500 K
Figure 20. Port 2 Configuration
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DS97Z8X0500
Zilog Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33-P30) and four fixed outputs (P37-P34). These eight lines can be configured by software for interrupt and handshake control functions. Port 3, Pin 0 is Schmitt- triggered. P31, P32 and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36 and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D0 to 1 state. For the interrupt function, P30 and P33 are falling edge triggered interrupt inputs. P31 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (Figure 21). Access to Counter/Timer 1 is made through P31 (TIN) and P36 (TOUT). Handshake lines for Port 0, Port 1, and Port 2 are also available on Port 3 (Table 9).
Z86E30/E31/E40 Z8 4K OTP Microcontroller Note: P33-P30 differs from the Z86C30/C31/C40 in that there is no clamping diode to VCC due to the EPROM highvoltage circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode.
1
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PRELIMINARY
29
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Z86E40 MCU
Port 3 (I/O or Control)
Auto Latch
P30 R247 = P3M
R 500 K
P30 Data Latch IRQ3 1 = Analog 0 = Digital
D1
DIG. P31 (AN1) IRQ2, Tin, P31 Data Latch
+ -
AN.
P32 (AN2)
IRQ0, P32 Data Latch
+
P33 (REF)
-
From Stop Mode Recovery Source
IRQ1, P33 Data Latch
Figure 21. Port 3 Configuration
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Zilog Table 9. Port 3 Pin Assignments Pin P30 P31 P32 P33 P34 P35 P36 P37 I/O IN IN IN IN OUT OUT OUT OUT CTC1 TIN Analog AN1 AN2 REF AN1-Out TOUT An2-Out
s s
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Interrupt IRQ3 IRQ2 IRQ0 IRQ1
P0 HS
P1 HS D/R
P2 HS
Ext
1
D/R D/R R/D R/D R/D /DM
Comparator Inputs. Port 3, P31, and P32, each have a comparator front end. The comparator reference voltage P33 is common to both comparators. In analog mode, P31 and P32 are the positive input of the comparators and P33 is the reference voltage of the comparators. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33-P31) that are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Auto Latches are available on Port 0, Port 2, and P30. There are no Auto Latches on P31, P32, and P33. Low EMI Emission. The Z86E40 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently. Use of this feature results in:
The pre-drivers slew rate reduced to 10 ns typical. Low EMI output drivers have resistance of 200 Ohms (typical). Low EMI Oscillator. Internal SCLK/TCLK= XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time, when Low EMI Oscillator is selected and system clock (SCLK = XTAL, SMR Reg. Bit D1 =1). Note for emulation only: Do not set the emulator to emulate Port 1 in low EMI mode. Port 1 must always be configured in Standard Mode.
s s
s
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
FUNCTIONAL DESCRIPTION
The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watch-Dog Timer 3. STOP-Mode Recovery Source Note: Having the Auto Power-on Reset circuitry built-in, the MCU does not need to be connected to an external power-on reset circuit. The reset time is 5 ms (typical). The MCU does not re-initialize WDTMR, SMR, P2M, and P3M registers to their reset values on a STOP-Mode Recovery operation. Note: The device VCC must rise up to the operating VCC specification before the TPOR expires. Program Memory. The MCU can address up to 4 KB of Internal Program Memory (Figure 22). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 12 (000CH) to address 4095 (0FFFH) consists of programmable EPROM. After reset, the program counter points at the address 000CH, which is the starting address of the user program. In ROMless mode, the Z86E40 can address up to 64 KB of External Program Memory. The ROM/ROMless option is only available on the 44-pin devices.
65535
EPROM External ROM and RAM On-Chip One Time PROM
ROMless
4096 4095 Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0
External ROM and RAM
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Figure 22. Program Memory Map (ROMless Z86E40 Only)
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Zilog EPROM Protect. When in ROM Protect Mode, and executing out of External Program Memory, instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. When in ROM Protect Mode and executing out of Internal Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. Data Memory (/DM). In EPROM Mode, the Z86E40 can address up to 60 KB of external data memory beginning at
Z86E30/E31/E40 Z8 4K OTP Microcontroller location 4096. In ROMless mode, the Z86E40 can address up to 64 KB of data memory. External data memory may be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 23). The state of the /DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references data (/DM active Low) memory.
1
EPROM 65535
ROMless
External Data Memory
External Data Memory
4096 4095 Not Addressable 0
Figure 23. Data Memory Map
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space R0 through R15 is implemented as 16 groups of 16 registers per group (Figure 26). These register groups are known as the Expanded Register File (ERF). The low nibble (D3-D0) of the Register Pointer (RP) select the active ERF group, and the high nibble (D7-D4) of register RP select the working register group. Three system configuration registers reside in the Expanded Register File at bank FH: PCON, SMR, and WDTMR. The rest of the Expanded Register is not physically implemented and is reserved for future expansion.
Zilog Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration registers in the expanded register group. The instructions can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 24). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Bank E0-EF can only be accessed through working register and indirect addressing modes. (This bank is available in Z86E30/E40 only.)
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Group Working Register Group Default setting after RESET = 00000000
Figure 24. Register Pointer Register
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
1
r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF
Register Group F
F0 EF 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F
Note: Registers 80H through EFH are available in the Z86C30 only.
Specified Working Register Group
The lower nibble of the register file address provided by the instruction points to the specified register.
Register Group 1
10 0F
R15 to R0 R15 to R4* R3 to R0*
Register Group 0
00
I/O Ports * Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP).
Figure 25. Register Pointer
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Z8(R) STANDARD CONTROL REGISTERS RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER REGISTER POINTER
7 6 5 4 3 2 1 0 % FF % FE % FD % FC % FB % FA % F9 % F8 % F7 % F6 % F5 % F4 % F3 Z86E30/E40 Only % F2 % F1 % F0 SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR Reserved 0 0 0 U 0 0 U 0 0 1 U U U U 0 0 0 0 U U 0 U 1 0 1 U U U U 0 0 0 0 U U 0 U 0 0 1 U U U U 0 0 0 0 U U 0 U 0 0 1 U U U U 0 0 0 0 U U 0 U 1 0 1 U U U U 0 0 0 0 U U 0 U 1 0 1 U U U U 0 0 0 0 U U 0 U 0 0 1 U U 0 U 0 0 0 0 U U 0 U 1 0 1 0 U 0 U 0
Working Register Group Pointer
Expanded Register Group Pointer
* *
Z8 Reg. File
%FF %FO
EXPANDED REG. GROUP (F) REGISTER
RESET CONDITION
U U U 0 1 1 0 1
*
Z86E30/E40 Only %7F
% (F) 0F % (F) 0E
WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON
* **
% (F) 0D % (F) 0C % (F) 0B % (F) 0A % (F) 09
U
U
U
U
U
U
0
0
0
0
1
0
0
0
0
0
Reserved
% (F) 08 % (F) 07
%0F %00
% (F) 06 % (F) 05 % (F) 04 % (F) 03 % (F) 02 % (F) 01 % (F) 00
1
1
1
1
1
1
1
0
Notes: U = Unknown For Z86E40 (ROMless) reset condition: "10110110"
EXPANDED REG. GROUP (0) REGISTER
RESET CONDITION
1 U U U 1 U U U 1 U U U 1 U U U U U U U U U U U U U U U U U U U
* *
% (0) 03 % (0) 02 % (0) 01 % (0) 00
P3 P2 P1 P0
* Will not be reset with a STOP Mode Recovery ** Will not be reset with a STOP Mode Recovery, except Bit D0.
Figure 26. Expanded Register File Architecture
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Zilog General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. The register R254 is general-purpose on Z86E30/E31. R254 and R255 are set to 00H after any reset or STOP-Mode recovery. RAM Protect. The upper portion of the RAM's address spaces 80H to EFH (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R251) is used to turn off/on the RAM protect by loading a 0 or 1, respectively. A 1 in D6 indicates RAM Protect enabled. RAM Protect is not available on the Z86E31. Stack. The Z86E40 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254-R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096 to 65535 in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z86E30/E31/E40 that resides within the 236 general-purpose registers (R4-R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to 00H after any reset or STOPMode Recovery.
Z86E30/E31/E40 Z8 4K OTP Microcontroller Counter/Timers. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
1
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
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Zilog The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the
Z86E30/E31/E40 Z8 4K OTP Microcontroller internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 serves as a timer output (TOUT) through which T0, T1 or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1.
1
OSC Internal Data Bus Write /2 PRE0 Initial Value Register D0 (SMR) 6-Bit Down Counter 8-bit Down Counter T0 Initial Value Register T0 Current Value Register Write Read
D1 (SMR)
/ 16
/4
IRQ4
Internal Clock External Clock Clock Logic /4 6-Bit Down Counter 8-Bit Down Counter
/2
TOUT P36
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
T1 Initial Value Register Read
T1 Current Value Register
TIN P31
Internal Data Bus
Figure 27. Counter/Timer Block Diagram
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30) and two
Zilog in counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 10).
IRQ0 IRQ2 IRQ1, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7)
IRQ
IMR 6 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 28. Interrupt Block Diagram Table 10. Interrupt Types, Sources, and Vectors Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Source /DAV0, IRQ0 IRQ1 /DAV2, IRQ2, TIN IRQ3 T0 TI Vector Location 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 Comments External (P32), Rising/Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising/Falling Edge Triggered External (P30), Falling Edge Triggered Internal Internal
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Zilog When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin.
Z86E30/E31/E40 Z8 4K OTP Microcontroller Programming bits for the Interrupt Edge Select are located in bits D7 and D6 of the IRQ Register (R250). The configuration is shown in Table 11. Table 11. IRQ Register Configuration IRQ D7 0 0 1 1
Notes: F = Falling Edge R = Rising Edge
1
Interrupt Edge D6 0 1 0 1 P31 F F R R/F P32 F R F R/F
Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, RC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 10 KHz to 16 MHz max, with a series resistance (RS) less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to device pin Ground. The RC oscillator option can be selected in the programming mode. The RC oscillator configuration must be an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to Ground (Figure 29).
XTAL1 C1 C1 L XTAL2 C2 C2
XTAL1 C1 R XTAL2
XTAL1
XTAL1
XTAL2
XTAL2
Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * F = 8 MHz
LC C1, C2 = 22 pF L = 130 H * F = 3 MHz *
RC @ 5V Vcc (TYP) C1 = 100 pF R = 2K F = 6 MHz
External Clock
* Typical value including pin parasitics
Figure 29. Oscillator Configuration
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR timer allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power fail to Power OK status 2. STOP-Mode Recovery (if D5 of SMR=0) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is bypassed after STOP-Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. FF 7F
Zilog In order to enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode=FFH) immediately before the appropriate sleep instruction, that is: FF 6F NOP STOP or NOP HALT ; clear the pipeline ; enter STOP ;mode ; clear the pipeline ; enter HALT mode
STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. STOP mode is terminated by one of the following resets: either by WDT time-out, POR, a STOP-Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address 000CH. Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00 (Figure 30).
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output 0 Port 1 Open Drain 1 Port 1 Push-pull Active* 0 Port 0 Open Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* Low EMI Oscillator 0 Low EMI 1 Standard*
1
* Default Setting After Reset
Figure 30. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A "1" in this location brings the comparator outputs to P34 and P37, and a "0" releases the Port to its standard I/O configuration. The default value is 0. Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit (D1=0) or configured as push-pull active by setting this bit (D1=1). The default value is 1. Port 0 Open-Drain (D2). Port 0 can be configured as an open-drain by resetting this bit (D2=0) or configured as push-pull active by setting this bit (D2=1). The default value is 1. Low EMI Port 0 (D3). Port 0 can be configured as a Low EMI Port by resetting this bit (D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1.
Low EMI Port 1 (D4). Port 1 can be configured as a Low EMI Port by resetting this bit (D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1. Note: The emulator does not support Port 1 low EMI mode and must be set D4 = 1. Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1. Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1. Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscillator. A "1" in this location configures the oscillator with standard drive. While a "0" configures the oscillator with low noise drive, however, it does not affect the relationship of SCLK and XTAL. The low EMI 43
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Z86E30/E31/E40 Z8 4K OTP Microcontroller mode will reduce the drive of the oscillator (OSC). The default value is 1. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. STOP-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of STOP-Mode Recovery (Figure 31). All bits are Write Only
Zilog except bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4 of the SMR register specify the STOP-Mode Recovery Source. The SMR is located in Bank F of the Expanded Register Group at address 0BH.
SMR (F) 0B D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide by 16 0 OFF ** 1 ON External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR and/or External Reset * 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0:3 111 P2 NOR 0:7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low * 1 High Stop Flag 0 POR* 1 Stop Recovery
* Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery.
Figure 31. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which is Read-Only)
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Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of
Z86E30/E31/E40 Z8 4K OTP Microcontroller PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. STOP-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake up source of the STOP-Mode Recovery (Figure 32). Table 12 shows the SMR source selected with the setting of D2 to D4. P33P31 cannot be used to wake up from STOP mode when programmed as analog inputs. When the STOP-Mode Recovery sources are selected in this register then SMR2 register bits D0, D1 must be set to zero. Note: If the Port2 pin is configured as an output, this output level will be read by the SMR circuitry..
1
SMR2 D1 D0 00 VDD P20 SMR2 D1 D0 01 P20 SMR2 D1 D0 10
P23
P27
SMR D4 D3 D2 000 VDD SMR D4 0 0 0 D3 0 1 1 D2 SMR D4 D3 D2 1 100 0 1 P27 P23 P27 SMR D4 D3 D2 101 P20 SMR D4 D3 D2 110 P20 SMR D4 D3 D2 111
P30 P31 P32
P33
T POR o RESET Stop-Mode Recovery Edge Select (SMR) T P33 Data o Latch and IRQ1 P33 From Pads
MUX
Digital/Analog Mode Select (P3M)
Figure 32. STOP-Mode Recovery Source
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Table 12. STOP-Mode Recovery Source D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 SMR Source selection POR recovery only P30 transition P31 transition (Not in analog mode) P32 transition (Not in analog mode) P33 transition (Not in analog mode) P27 transition Logical NOR of Port 2 bits 0-3 Logical NOR of Port 2 bits 0-7
Zilog POR clock source is selected with bit 4 of the WDT register. Note: Execution of the WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. WDT Time-Out Period (D0 and D1). Bits 0 and 1 control a tap circuit that determines the time-out periods that can beobtained (Table 13). The default value of D0 and D1 are 1 and 0, respectively. Table 13. Time-out Period of WDT Time-out of Time-out of the Internal the System RC OSC Clock 5 ms 10 ms* 20 ms 80 ms 128 SCLK 256 SCLK* 512 SCLK 2048 SCLK
D1 0 0 1 1
D0 0 1 0 1
STOP-Mode Recovery Delay Select (D5). The 5 ms RESET delay after STOP-Mode Recovery is disabled by programming this bit to a zero. A 1 in this bit will cause a 5 ms RESET delay after STOP-Mode Recovery. The default condition of this bit is 1. If the fast wake up mode is selected, the STOP-Mode Recovery source needs to be kept active for at least 5TpC. STOP-Mode Recovery Level Select (D6). A 1 in this bit defines that a high level on any one of the recovery sources wakes the MCU from STOP mode. A 0 defines low level recovery. The default value is 0. Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A "0" in this bit indicates that the device has been reset by POR (cold). A "1" in this bit indicates the device was awakened by a SMR source (warm). STOP-Mode Recovery Register 2 (SMR2). This register contains additional Stop-Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR Register. Bits D2, D3, and D4 must be 0. SMR:10 D1 0 0 1 D0 0 1 0 Operation Description of Action POR and/or external reset recovery Logical AND of P20 through P23 Logical AND of P20 through P27
Notes: *The default setting is 10 ms.
WDT During HALT Mode (D2). This bit determines whether or not the WDT is active during HALT mode. A "1" indicates that the WDT is active during HALT. A "0" disables the WDT in HALT mode. The default value is 1. WDT During STOP Mode (D3). This bit determines whether or not the WDT is active during STOP mode. A 1 indicates active during STOP. A "0" disables the WDT during STOP mode. This is applicable only when the WDT clock source is the internal RC oscillator. Clock Source For WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1, and the WDT is stopped in STOP mode. The default configuration of this bit is 0, which selects the RC oscillator. Permanent WDT. When this feature is enabled, the WDT is enabled after reset and will operate in Run and Halt mode. The control bits in the WDTMR do not affect the WDT operation. If the clock source of the WDT is the internal RC oscillator, then the WDT will run in STOP mode. If the clock source of the WDT is the XTAL1 pin, then the WDT will not run in STOP mode. Note: WDT time-out in Stop-Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system clock cycles from the execution of the first instruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery DS97Z8X0500
Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On Reset and initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT is driven either by an on-board RC oscillator or an external oscillator from XTAL1 pin. The
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Zilog (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or otherwise. The
Z86E30/E31/E40 Z8 4K OTP Microcontroller WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location 0FH.
1
WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 01 * 10 11
INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0)
* Default setting after RESET
Figure 33. Watch-Dog Timer Mode Register Write Only
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
/Reset
4 Clock Filter
/Clear CLK
18 Clock RESET Generator
RESET
Internal /RESET WDT Select (WDTMR) CLK Source Select (WDTMR) XTAL Internal RC OSC. M U X 5ms POR 5ms 15ms 25ms 100ms CK WDT/POR Counter Chain /CLR WDT TAP SELECT
VDD VLV
+ -
2V Operating Voltage Det.
/WDT
From Stop Mode Recovery Source Stop Delay Select (SMR)
Figure 34. Resets and WDT Auto Reset Voltage. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC is below VLV (Figure 35). Note: VCC must be in the allowed operating range prior to the minimum Power-On Reset time-out (TPOR).
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
VCC (Volts)
3.7
1
3.5 3.3
3.1
2.9
2.7
2.5
2.3 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C)
Figure 35. Typical Z86E40 VLV Voltage vs Temperature
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Z86E30/E31/E40 Z8 4K OTP Microcontroller EPROM MODE. Table 14 shows the programming voltages of each programming mode. Table 15, Figures 38, 39, and 40 show the programming timing of each programming mode. Figure 41 shows the circuit diagram of a Z86E40 programming adaptor, which adapts from 2764A to Z86E40. Figure 43 shows the flow-chart of an Intelligent Programming Algorithm, which is compatible with 2764A EPROM (Z86E40 is 4K EPROM, 2764A is 8K EPROM). Since the EPROM size of Z86E30/E31/E40 differs from 2764A, the programming address range has to be set from 0000H to 0FFFH for the Z86E30/E40 and 0000H to 07FFH for Z86E31. Otherwise, the upper portion of EPROM data will overwrite the lower portion of EPROM data. Figure 39 shows the adaptation from the 2764A to Z86E30/E31. Note: EPROM Protect feature allows the LDC, LDCI, LDE, and LDEI instructions from internal program memory. A ROM look-up table can be used with this feature. During programming, the VPP input pin supplies the programming voltage and current to the EPROM. This pin is also used to latch which EPROM mode is to be used (R/W EPROM or R/W Option bits). The mode is set by placing the correct mode number on the least significant bits of the address and raising the EPM pin above V. After a setup time, the VPP pin can then be raised or lowered. The
Zilog latched EPROM mode will remain until the EPM pin is reduced below VH. Mode Name EPROM R/W Option Bit R/W Mode # 0 3 LSB Addr 0000 0011
EPROM R/W mode allows the programming of the user mode program ROM. Option Bit R/W allows the programming of the Z8 option bits. When the device is latched into Option Bit R/W mode, the address must then be changed to 63 decimals (000000111111 Binary). The Options are mapped into this address as follows: Bit 7 6 5 4 3 2 1 0 Option Unused Unused 32 KHz XTAL Option Permanent WDT Auto Latch Disable RC Oscillator Option RAM Protect ROM Protect
Table 14 gives the proper conditions for EPROM R/W operations, once the mode is latched. Table 14. EPROM Programming Table Programming Modes EPROM READ1 EPROM READ2 PROGRAM PROGRAM VERIFY OPTION BIT PGM OPTION BIT READ VPP X X VPP VPP VPP X EPM VH VH VH VH VH VH /CE VIL VIL VIL VIL VIL VIL /OE VIL VIL VIH VIL VIH VIL /PGM VIH VIH VIL VIH VIL VIH ADDR ADDR ADDR ADDR ADDR 63 63 DATA Out Out In Out IN OUT VCC* 4.5V 5.5V 6.4V 6.0V 6.4V 6.0V
Notes: VH = 13.0 V 0.1 V VIH = As per specific Z8 DC specification. VIL= As per specific Z8 DC specification. X=Not used, but must be set to VH, VIH, or VIL level. NU = Not used, but must be set to either VIH or VIL level. IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum. *VCC has a tolerance of 0.25V. Zilog recommends an EPROM read at VCC = 4.5 V and 5.5 V to ensure proper device operations during the VCC after programming, but VCC = 5.0 V is acceptable.
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Zilog Table 15. EPROM Programming Timing Parameters 1 2 3 4 5 6 7 8 9 10 11 Name Address Setup Time Data Setup Time VPP Setup VCC Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time /OE Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width/Option Program Pulse Width EPM Setup Time /PGM Setup Time Address to /OE Setup Time /OE Width Address to /OE Low Min 2 2 2 2 2 0.95 2 2 200 2.85 1.05 Max
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Units s s s s s ms s s ns ns ms
1
100
12 13 14 15 16
2 2 2 250 125
s s s ns ns
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Zilog
VIH Address VIL VIH Data VIL VH VPP VIL VH EPM VIL
12 16
Address Stable
Address Stable
Invalid
9
Valid
Invalid
Valid
5.5V
VCC
4.5V VIH
/CE
VIL VIH
5 15
/OE
VIL VIH
15 15
/PGM
VIL
3
Figure 36. EPROM Read Mode Timing Diagram
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
Z86E40 TIMING DIAGRAMS
VIH Address VIL VIH Data VIL
1
1
Address Stable
Data Stable
2 9
Data Out Valid
10
VH VPP VIH
3
VH EPM VIL 6V VCC 4.5V VIH /CE VIL
5 4 7
VIH /OE VIL VIH /PGM VIL
6 11 Program Cycle Verify Cycle 8 15
Figure 37. Timing Diagram of EPROM Program and Verify Modes
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
U1 D0 D1 D2 D3 D4 D5 D6 D7 35 36 37 38 39 2 3 4 P20 P21 P22 P23 P24 P25 P26 P27 P10 P11 28 29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A0 A1 A2 A3 A4 A5 A6 A7 26 27 30 34 5 6 7 10 1 20 40 GND 21 P00 P01 P02 P03 P04 P05 P06 P07 R//W /AS /DS /RESET XTAL1 XTAL2 14 P30 P31 P32 P33 P34 P35 P36 P37 25 /PGM 16 /0E 17 18 19 22 24 23 31 11 15 EPM VPP A8 A9 A10 A11 GND VCC /CE 1 KOhm 1 1 KOhm 1 R2 R1 2 2 A9 A10 A11 10 9 8 7 6 5 4 3 A0 A1 A2 A3 A4 A5 A6 A7
U2 00 01 02 11 12 13 D0 D1 D2 D3 D4 D5 D6 D7
P12 32 33 P13 8 P14 9 P15 12 P16 13 P17
03 15 16 04 17 05 06 18 07 19
25 A8 24 21 23 2 27 20 22 A9 A10 A11 A12 /PGM /CS /OE GND 14 VCC 28 VPP 1 2 GND VCC VPP
2764 Pins C1
0.01F 1 GND
Z86E40 40-Pin DIP Socket U3
12.5V
0.1F C2 2 1
1
R4
2
1N5243 1
1
R3
2
1 KOhm
10 KOhm
D1 2
12.5V 16
X1
D1 1 EPM
GND
GND 2 1
12.5 Volt
GND
4
X3
D3 3
P1
VCC 15 IX1 4 X 5 X 10 X S2 D2 3
5.0V
1N5231
1 1 KOhm
D2 1
R5
2
X
S4
D4 6
X
GND
IX2 VCC 5.0 V
IH5043
Figure 38. Z86E40 Z8 OTP Programming Adapter For use with Standard EPROM Programmers
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
U1 D0 D1 D2 D3 D4 D5 D6 D7 24 25 26 27 28 1 2 3 P20 P21 P22 P23 P24 P25 P26 P27 18 11 12 13 14 15 17 16 /PGM /OE EPM VPP A8 A9 A10 A11 1 KOhm 1 1 KOhm 1 R2 R1 2 2 A0 A1 A2 A3 A4 A5 A6 A7 A4 A0 A1 A2 A3 A4 A5 A6 A7 19 20 21 23 4 5 6 7 P00 P01 P02 P03 P04 P05 P06 P07 P30 P31 P32 P33 P34 P35 P36 P37 A5 A6 A7 10 9 8 7 6 5 4 3 A0 A1 A2 A3 A4 A5 A6
U2 00 01 02 11 12 13 D0 D1 D2 D3 D4 D5 D6 D7
1
03 15 16 04 17 05 18 06 19 07
A7 25 A8 24 A9 21 A10 23 A11 2 A12 27 /PGM 20 22 /CS /OE
GND 14 VCC 28 VPP 1
GND VCC VPP
2764 Pins
C1
2
0.01F
XTAL1 XTAL2
9 GND
Z86E30/31 28-Pin DIP Socket
12.5V
1
R4
2
1
R3
2
0.1F C2 2 1
1N5243
1
1 KOhm
10 KOhm
U3 12.5V 16 X1 D1 1 EPM GND 4 X3 D3 3
GND
2
GND 2 1
D1
1
12.5 Volt
10
/CE
P1
5.0V 1 R5 2 1 KOhm
VCC 15 IX1
1N5231
1 2
4 X 5 X 10 X
S2
D2 3
X
S4
D4 6
GND X
IX2
VCC
5.0 V
IH5043
Note: The programming address must be set to 0000H - 0FFFH (Lower 4K Byte Memory). For Z86E30 0000H - 07FFH (Lower 2K Byte Memory). For Z86E31
Figure 39. Z86E30/E31 Programming Adaptor Circuitry
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PRELIMINARY
D2
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Start
Addr = First Location
Vcc = 6.0V Vpp = 12.5V
N=0
Program 1 ms Pulse
Increment N
Yes N = 25 ? No Fail Verify One Byte Pass Prog. One Pulse 3xN ms Duration Fail Verify Byte Pass
Increment Address
No Last Addr ? Yes
Vcc = Vpp = 4.5V *
Note: * To ensure proper operaton, Zilog recommends Vcc range of the device Vcc specification, But Vcc = 5.0V is acceptable.
Verify All Bytes Pass
Fail
Vcc = Vpp = 5.5V *
Device Failed
Verify All Bytes Pass
Fail
Device Passed
Figure 40. Z86E40 Programming Algorithm
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
EXPANDED REGISTER FILE CONTROL REGISTERS
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0
1
WDT TAP 00 01 * 10 11 INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK
Comparator Output Port 3 0 P34, P37 Standard* 1 P34, P37 Comparator Output 0 Port 1 Open-Drain 1 Port 1 Push-Pull Active* 0 Port 0 Open-Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* Low EMI Oscillator 0 Low EMI 1 Standard*
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0)
* Default setting after RESET
* Default Setting After Reset Must Be 1 for Z86E30/E31
Figure 43. Watch-Dog Timer Mode Register Write Only
Figure 41. Port Configuration Register Write Only
SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR Only and/or External Reset* 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low* 1 High Stop Flag 0 POR* 1 Stop Recovery
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2 00 POR only* 01 AND P20,P21,P22,P23 10 AND P20,P21,P22,P23,P24, P25,P26,P27 Reserved (Must be 0)
Figure 44. STOP-Mode Recovery Register 2 Write Only
* Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery.
Figure 42. STOP-Mode Recovery Register Write Only Except Bit D7, Which is Read Only
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Z8 CONTROL REGISTER DIAGRAMS
R240 D7 D6 D5 D4 D3 D2 D1 D0
R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Count Mode 0 T1 Single Pass* 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN Mode) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) *Default After Reset
Figure 45. Reserved
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0
0 No Function* 1 Load T0 0 Disable T0 Count* 1 Enable T0 Count 0 No Function* 1 Load T1 0 Disable T1 Count* 1 Enable T1 Count TIN Modes 00 External Clock Input* 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used* 01 T0 Out 10 T1 Out 11 Internal Clock Out Default After Reset = 00H
R245 PRE0
R244 T0
Figure 48. Prescaler 1 Register F3H: Write Only
D7 D6 D5 D4 D3 D2 D1 D0
T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read)
Figure 49. Counter/Timer 0 Register F4H; Read/Write
Figure 46. Timer Mode Register F1H: Read/Write
D7 D6 D5 D4 D3 D2 D1 D0
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
Count Mode 0 T1 Single Pass 1 T1 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read)
Figure 50. Prescaler 0 Register F5H: Write Only
Figure 47. Counter/Timer 1 Register F2H: Read/Write
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
1
P03 - P00 Mode 00 Output 01 Input 1X A11 - A8 Stack Selection 0 External 1 Internal P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7 - AD0 11 High-Impedance AD7 - AD0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected External Memory Timing 0 Normal 1 Extended
* Default After Reset
P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input*
Figure 51. Port 2 Mode Register F6H: Write Only
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain 1 Port 2 Push-pull Active 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = /DM P33 = /DAV1/RDY1 P34 = RDY1//DAV1
Reset Condition = 0100 1101B For ROMless Condition = 1011 0110B Z86E30/E31 Must be 00
P07 - P04 Mode 00 Output 01 Input 1X A15 - A12
Figure 53. Port 0 and 1 Mode Register F8H: Write Only Z86E30/E31 Only
0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 P30 = Input P37 = Output Reserved (Must be 0) Default After Reset = 00H Z86E30/E31 Must Be 00
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0
Figure 52. Port 3 Mode Register F7H: Write Only
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0)
Figure 54. Interrupt Priority Register F9H: Write Only
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P30 Input IRQ4 = T0 IRQ5 = T1 Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11
Expanded Register File Working Register Pointer Default After Reset = 00H
Figure 58. Register Pointer FDH: Read/Write
Default After Reset = 00H
R254 SPH
Figure 55. Interrupt Request Register FAH: Read/Write
D7 D6 D5 D4 D3 D2 D1 D0
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
(Z86E40) Stack Pointer Upper Byte (SP8 - SP15) (Z86E30/E31) 0 = 0 State 1 = 1 State
1 Enables IRQ5-IRQ0 (D0 = IRQ0) 1 Enables RAM Protect 1 Enables Interrupts
Figure 59. Stack Pointer High FEH: Read/Write
This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently.
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
Figure 56. Interrupt Mask Register FBH: Read/Write
Stack Pointer Lower Byte (SP0 - SP7)
R252 FLAGS D7 D6 D5 D4 D3 D2 D1 D0
Figure 60. Stack Pointer Low FFH: Read/Write
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 57. Flag Register FCH: Read/Write
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
PACKAGE INFORMATION
1
Figure 61. 40-Pin DIP Package Diagram
Figure 62. 44-Pin PLCC Package Diagram
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Figure 63. 44-Pin QFP Package Diagram
Figure 64. 40-Pin Cerdip Window Lid Package Diagram
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DS97Z8X0500
Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
1
Figure 65. 28-Pin DIP Package Diagram
Figure 66. 28-Pin Window Cerdip Package Diagram
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
Figure 67. 18-Pin SOIC Package Diagram
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Zilog
Z86E30/E31/E40 Z8 4K OTP Microcontroller
ORDERING INFORMATION Z86E40 (16 MHz)
40-Pin Cerdip Window Lid Z86E4016ESE Z86E4016ESE
1
44-Pin QFP Z86E4016FSC Z86E4016FEC
40-Pin DIP Z86E4016PSC Z86E4016PEC Z86E30 (16 MHz) 28-Pin DIP Z86E3016PSC Z96E3016PEC
44-Pin PLCC Z86E4016VSC Z86E4016VEC
28-Pin Cerdip Window Lid Z86E3016ESE Z86E3016SSC Z86E3016SEC
Z86E31 (16 MHz) 28-Pin DIP Z86E3116PSC 28-Pin Cerdip Window Lid Z86E3116SSC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Package
P = Plastic DIP V = Plastic Chip Carrier F = Plastic Quad Flat Pack K = Cerdip Window Lid
Temperature
S = 0 C to +70 C E = -40 C to +105 C
Speed
16 = 16 MHz
Environmental
C= Plastic Standard E = Hermetic Standard
Example:
Z 86E40 16 P S C is a Z86E40, 16 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix
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Z86E30/E31/E40 Z8 4K OTP Microcontroller
Zilog
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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